An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform

A high speed and reduced-area 2-D discrete wavelet transform (2-D DWT) architecture is proposed and the design is simulated. Initially modifications are made to the lifting scheme, and the intermediate results are recombined and stored to reduce the number of pipelining stages. The architecture uses three basic 1D-DWT image processing elements. The proposed architecture only requires less registers between the row and column filters as the transposing buffer, and a higher efficiency can be achieved with reduced delay.